| An architectural solution for the inductive noise problem due to clock-gating.doc |
Download |
| An architectural solution for the inductive noise problem due to clock-gating.pdf |
Download |
| An architectural solution for the inductive noise problem due to clock-gating.ppt |
Download |
| An architectural solution for the inductive noise problem due to clock-gating.txt |
Download |
| An architectural solution for the inductive noise problem due to clock-gating.lit |
Download |
| An architectural solution for the inductive noise problem due to clock-gating.prc |
Download |
| An architectural solution for the inductive noise problem due to clock-gating.pdb |
Download |
| An architectural solution for the inductive noise problem due to clock-gating.rb |
Download |
| An architectural solution for the inductive noise problem due to clock-gating.chm |
Download |
| Clock distribution using multiple voltages.doc |
Download |
| Clock distribution using multiple voltages.pdf |
Download |
| Clock distribution using multiple voltages.ppt |
Download |
| Clock distribution using multiple voltages.txt |
Download |
| Clock distribution using multiple voltages.lit |
Download |
| Clock distribution using multiple voltages.prc |
Download |
| Clock distribution using multiple voltages.pdb |
Download |
| Clock distribution using multiple voltages.rb |
Download |
| Clock distribution using multiple voltages.chm |
Download |
| On the interaction of power distribution network with substrate.doc |
Download |
| On the interaction of power distribution network with substrate.pdf |
Download |
| On the interaction of power distribution network with substrate.ppt |
Download |
| On the interaction of power distribution network with substrate.txt |
Download |
| On the interaction of power distribution network with substrate.lit |
Download |
| On the interaction of power distribution network with substrate.prc |
Download |
| On the interaction of power distribution network with substrate.pdb |
Download |
| On the interaction of power distribution network with substrate.rb |
Download |
| On the interaction of power distribution network with substrate.chm |
Download |
| Low-power mapping of behavioral arrays to multiple memories.doc |
Download |
| Low-power mapping of behavioral arrays to multiple memories.pdf |
Download |
| Low-power mapping of behavioral arrays to multiple memories.ppt |
Download |
| Low-power mapping of behavioral arrays to multiple memories.txt |
Download |
| Low-power mapping of behavioral arrays to multiple memories.lit |
Download |
| Low-power mapping of behavioral arrays to multiple memories.prc |
Download |
| Low-power mapping of behavioral arrays to multiple memories.pdb |
Download |
| Low-power mapping of behavioral arrays to multiple memories.rb |
Download |
| Low-power mapping of behavioral arrays to multiple memories.chm |
Download |
| Model and analysis for combined package and on-chip power grid simulation.doc |
Download |
| Model and analysis for combined package and on-chip power grid simulation.pdf |
Download |
| Model and analysis for combined package and on-chip power grid simulation.ppt |
Download |
| Model and analysis for combined package and on-chip power grid simulation.txt |
Download |
| Model and analysis for combined package and on-chip power grid simulation.lit |
Download |
| Model and analysis for combined package and on-chip power grid simulation.prc |
Download |
| Model and analysis for combined package and on-chip power grid simulation.pdb |
Download |
| Model and analysis for combined package and on-chip power grid simulation.rb |
Download |
| Model and analysis for combined package and on-chip power grid simulation.chm |
Download |
| A low-power clock and data recovery circuit for 2.5 Gb/s SDH receivers.doc |
Download |
| A low-power clock and data recovery circuit for 2.5 Gb/s SDH receivers.pdf |
Download |
| A low-power clock and data recovery circuit for 2.5 Gb/s SDH receivers.ppt |
Download |
| A low-power clock and data recovery circuit for 2.5 Gb/s SDH receivers.txt |
Download |
| A low-power clock and data recovery circuit for 2.5 Gb/s SDH receivers.lit |
Download |
| A low-power clock and data recovery circuit for 2.5 Gb/s SDH receivers.prc |
Download |
| A low-power clock and data recovery circuit for 2.5 Gb/s SDH receivers.pdb |
Download |
| A low-power clock and data recovery circuit for 2.5 Gb/s SDH receivers.rb |
Download |
| A low-power clock and data recovery circuit for 2.5 Gb/s SDH receivers.chm |
Download |
| Oversampled gain-boosting.doc |
Download |
| Oversampled gain-boosting.pdf |
Download |
| Oversampled gain-boosting.ppt |
Download |
| Oversampled gain-boosting.txt |
Download |
| Oversampled gain-boosting.lit |
Download |
| Oversampled gain-boosting.prc |
Download |
| Oversampled gain-boosting.pdb |
Download |
| Oversampled gain-boosting.rb |
Download |
| Oversampled gain-boosting.chm |
Download |
| Reducing access energy of on-chip data memory considering active data bitwidth.doc |
Download |
| Reducing access energy of on-chip data memory considering active data bitwidth.pdf |
Download |
| Reducing access energy of on-chip data memory considering active data bitwidth.ppt |
Download |
| Reducing access energy of on-chip data memory considering active data bitwidth.txt |
Download |
| Reducing access energy of on-chip data memory considering active data bitwidth.lit |
Download |
| Reducing access energy of on-chip data memory considering active data bitwidth.prc |
Download |
| Reducing access energy of on-chip data memory considering active data bitwidth.pdb |
Download |
| Reducing access energy of on-chip data memory considering active data bitwidth.rb |
Download |
| Reducing access energy of on-chip data memory considering active data bitwidth.chm |
Download |
| Future directions in clocking multi-ghz systems.doc |
Download |
| Future directions in clocking multi-ghz systems.pdf |
Download |
| Future directions in clocking multi-ghz systems.ppt |
Download |
| Future directions in clocking multi-ghz systems.txt |
Download |
| Future directions in clocking multi-ghz systems.lit |
Download |
| Future directions in clocking multi-ghz systems.prc |
Download |
| Future directions in clocking multi-ghz systems.pdb |
Download |
| Future directions in clocking multi-ghz systems.rb |
Download |
| Future directions in clocking multi-ghz systems.chm |
Download |
| Optimizing the DRAM refresh count for merged DRAM/logic LSIs.doc |
Download |
| Optimizing the DRAM refresh count for merged DRAM/logic LSIs.pdf |
Download |
| Optimizing the DRAM refresh count for merged DRAM/logic LSIs.ppt |
Download |
| Optimizing the DRAM refresh count for merged DRAM/logic LSIs.txt |
Download |
| Optimizing the DRAM refresh count for merged DRAM/logic LSIs.lit |
Download |
| Optimizing the DRAM refresh count for merged DRAM/logic LSIs.prc |
Download |
| Optimizing the DRAM refresh count for merged DRAM/logic LSIs.pdb |
Download |
| Optimizing the DRAM refresh count for merged DRAM/logic LSIs.rb |
Download |
| Optimizing the DRAM refresh count for merged DRAM/logic LSIs.chm |
Download |